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For a given vector and fault, the output pins that are expected to fail can be looked up in this dictionary In a testing scenario, we take a failing test vector and list of failed output pins, and attempt to look up a fault (or faults) that match the failed pin behavior for that vector Fault dictionaries work well when actual defects that cause a circuit to fail closely match the fault model When defects occur that vary from the modeled faults, then a dictionary lookup may come up empty (no matching fault), or matches may be found but point to the wrong faults, or so many matches may be found that it is impractical to examine them all to see which (if any) are the actual problem Dictionary generation is computationally intensive, dictionaries may consume huge amounts of storage space,* and dictionary lookups may not work.
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This technology was invented along with small-scale integrated bipolar technologies such as early TTL or ECL The advent of large-scale integration and CMOS technology has made fault dictionary technology nearly useless in board testing practice Performance testers are intended to emulate the environment the board would encounter in its native application This means the tester itself needs to be carefully customized to supply this environment, or it must be a general-purpose tester with a great degree of flexibility Flexibility brings cost, so commercial functional testers tend to be among the most expensive Programming such machines is a complex task, due both to the flexibility of the tester and to the nature of the test requirements It is difficult at best to get automated support for functional test programming Typically, such programming takes extreme patience and a high level of skill again, two more costs.
To compound this, any last-minute design changes to the board may cause expensive and time-consuming test modifications or invalidate the tests altogether..
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Testing Boards for Manufacturing Defects Manufacturing defects can be detected by a functional test, but because functional testers are expensive and difficult to program, other techniques have arisen to test for them. These testers have one or more of the following advantages: 1. They are much easier to program, often requiring less than 10 percent of the time of functional test development. 2. Automatic test program generators that analyze the circuit design database do most of the work and relieve the skill required of the programmer. 3. Their programs are much less sensitive to design changes because they take a divide-andconquer approach; the effects of design changes are localized, requiring that only a portion of the test be reprogrammed. 4. They offer much better defect resolution for many defects because localized portions of the circuit are being analyzed, reducing diagnostic complexity. The principal technology is the in-circuit tester. This tester utilizes a high degree of nodal access that is, connection to printed circuit traces to perform its work. Nodal access is provided by a unique fixture called the bed of nails. (See Fig. 55.4.) This fixture is made up of a platen that supports the board under test. The platen is drilled with holes below each target point for nodal access. In the holes are spring-loaded nails that contact the target points on
* For example, say a circuit has 100,000 gates. The number of stuck-at faults to be simulated may easily be 200,000. A set of test vectors for these may easily exceed 500,000. If the circuit has a fairly normal complement of 250 outputs, then a fault dictionary for this example would consume the product of faults times vectors times outputs (2.5 1013 bits, or about 3.125 terabytes, give or take a gigabyte). Fault simulation times lasting months, even on very fast computers, have been reported. Of course, larger circuits will need more! CMOS VLSI circuits have several defect modes that are inconvenient to model in popular fault simulators, and thus fault models are more likely not to match defects. Two of the offending defect modes are bridging faults (intermetal shorts) and metallization opens that may actually introduce capacitive memory into a circuit. These are difficult to represent with traditional fault-modeling techniques.
FIGURE 55.4 Cutaway drawing of a board resting on top of an in-circuit vacuum-actuated fixture, the bed of nails. The interface pins (the mechanical interface to the ATE pin electronics) are placed very close to reduce path lengths.
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